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AI Prompts for RTL Design, Verification & EDA Automation
Select a category or browse all VLSI & hardware design prompts below
1. Verilog Module Structure Draft
RTL DESIGNDraft a Verilog module skeleton for a given function.
Act as an RTL design assistant. Draft a Verilog module skeleton
for [function, e.g. an 8-bit synchronous counter with enable and
reset]. Include port list, parameter declarations, internal
signal naming, and comments describing intended behavior for
each block.
Act as an RTL design assistant. Draft a Verilog module skeleton
for [function, e.g. an 8-bit synchronous counter with enable and
reset]. Include port list, parameter declarations, internal
signal naming, and comments describing intended behavior for
each block.
2. SystemVerilog Interface Design
RTL DESIGNDraft a SystemVerilog interface for module communication.
Draft a SystemVerilog interface definition for connecting
[module A] and [module B] using a
[protocol, e.g. AXI-Stream, simple handshake]. Include signal
declarations, modport definitions, and comments on handshake
timing expectations.
Draft a SystemVerilog interface definition for connecting
[module A] and [module B] using a
[protocol, e.g. AXI-Stream, simple handshake]. Include signal
declarations, modport definitions, and comments on handshake
timing expectations.
3. FSM (Finite State Machine) Design Outline
RTL DESIGNStructure an FSM before writing the RTL code.
Design a finite state machine for [describe control behavior,
e.g. a UART transmitter sequence]. List each state, the
transition conditions, and outputs asserted in each state, in a
table format ready to translate into Verilog/SystemVerilog.
Design a finite state machine for [describe control behavior,
e.g. a UART transmitter sequence]. List each state, the
transition conditions, and outputs asserted in each state, in a
table format ready to translate into Verilog/SystemVerilog.
4. Clock Domain Crossing (CDC) Review
RTL DESIGNReview a design for clock domain crossing hazards.
Review this design description for clock domain crossing risks:
[describe signal paths between clock domains].
Identify signals that need synchronizers, recommend a
synchronization scheme (2-flop, handshake, FIFO), and note
where metastability risks are highest.
Review this design description for clock domain crossing risks:
[describe signal paths between clock domains].
Identify signals that need synchronizers, recommend a
synchronization scheme (2-flop, handshake, FIFO), and note
where metastability risks are highest.
5. Pipeline Stage Design Draft
RTL DESIGNStructure a pipelined datapath before coding it.
Draft a pipeline stage breakdown for [describe function, e.g. a
5-stage RISC processor datapath]. Include what happens in each
stage, register boundaries between stages, and hazard types
(structural, data, control) to consider.
Draft a pipeline stage breakdown for [describe function, e.g. a
5-stage RISC processor datapath]. Include what happens in each
stage, register boundaries between stages, and hazard types
(structural, data, control) to consider.
6. FIFO Design Specification
RTL DESIGNDraft a specification for a FIFO buffer module.
Draft a specification for a [synchronous/asynchronous] FIFO of
depth [depth] and width [bit width]. Include port list,
full/empty flag logic, and (if asynchronous) the CDC approach
for the read/write pointers.
Draft a specification for a [synchronous/asynchronous] FIFO of
depth [depth] and width [bit width]. Include port list,
full/empty flag logic, and (if asynchronous) the CDC approach
for the read/write pointers.
7. RTL Code Review Checklist
RTL DESIGNReview RTL code for common coding style issues.
Create an RTL code review checklist for
[Verilog/SystemVerilog] design files. Include latch inference
risks, blocking vs. non-blocking assignment usage, reset
strategy consistency, and naming convention items to check.
Create an RTL code review checklist for
[Verilog/SystemVerilog] design files. Include latch inference
risks, blocking vs. non-blocking assignment usage, reset
strategy consistency, and naming convention items to check.
8. Memory Controller Interface Draft
RTL DESIGNDraft an interface concept for a memory controller.
Draft an interface specification for a memory controller
connecting to [memory type, e.g. DDR3, SRAM] supporting
[data width/burst length]. Include command signals, timing
parameters to reference from the datasheet, and typical
handshake sequence.
Draft an interface specification for a memory controller
connecting to [memory type, e.g. DDR3, SRAM] supporting
[data width/burst length]. Include command signals, timing
parameters to reference from the datasheet, and typical
handshake sequence.
9. Low-Power Design Strategy Overview
RTL DESIGNSummarize low-power design techniques for a block.
Summarize low-power design strategies (clock gating, power
gating, multi-Vt cells) applicable to [design block description]
targeting [power budget]. Include trade-offs in area, timing,
and verification complexity for each strategy.
Summarize low-power design strategies (clock gating, power
gating, multi-Vt cells) applicable to [design block description]
targeting [power budget]. Include trade-offs in area, timing,
and verification complexity for each strategy.
10. Testbench Architecture Outline
VERIFICATIONStructure a UVM/testbench architecture for a DUT.
Outline a testbench architecture for verifying
[DUT description, e.g. an AXI slave module]. Include driver,
monitor, scoreboard, and sequencer components (UVM-style if
applicable), and how they connect to the DUT interface.
Outline a testbench architecture for verifying
[DUT description, e.g. an AXI slave module]. Include driver,
monitor, scoreboard, and sequencer components (UVM-style if
applicable), and how they connect to the DUT interface.
11. Test Plan Draft
VERIFICATIONDraft a verification test plan for a design block.
Draft a verification test plan for [design block description].
Include functional features to verify, corner cases, error
injection scenarios, and coverage goals (functional and code
coverage) to track completeness.
Draft a verification test plan for [design block description].
Include functional features to verify, corner cases, error
injection scenarios, and coverage goals (functional and code
coverage) to track completeness.
12. Constrained Random Testing Strategy
VERIFICATIONPlan a constrained random verification approach.
Design a constrained random testing strategy for
[DUT description]. Include the input variables to randomize,
constraints needed to keep stimuli legal, and how to weight
scenarios to hit important corner cases more often.
Design a constrained random testing strategy for
[DUT description]. Include the input variables to randomize,
constraints needed to keep stimuli legal, and how to weight
scenarios to hit important corner cases more often.
13. Assertion (SVA) Draft Outline
VERIFICATIONPlan SystemVerilog assertions for a protocol check.
Outline SystemVerilog assertions needed to check
[protocol/behavior, e.g. a valid-ready handshake] on
[interface description]. Describe each assertion in plain
language (property being checked, trigger condition) before
converting to SVA syntax.
Outline SystemVerilog assertions needed to check
[protocol/behavior, e.g. a valid-ready handshake] on
[interface description]. Describe each assertion in plain
language (property being checked, trigger condition) before
converting to SVA syntax.
14. Functional Coverage Model Draft
VERIFICATIONPlan a functional coverage model for a DUT.
Draft a functional coverage model for [DUT description].
Include coverpoints for key variables, cross-coverage between
related signals, and bins that represent important corner-case
values to track.
Draft a functional coverage model for [DUT description].
Include coverpoints for key variables, cross-coverage between
related signals, and bins that represent important corner-case
values to track.
15. Debugging Waveform Analysis Approach (AI-Trace-Assisted)
VERIFICATIONStructure a debugging approach, including where an autonomous waveform-tracing agent now fits before you dig in by hand.
Help me structure a debugging approach for a failing simulation
where [describe symptom, e.g. output signal doesn't match
expected value at time X]. Suggest which signals to trace first,
likely root cause categories, and how to narrow down the issue
systematically, and note where an AI/LLM-based waveform-tracing
agent (AST-based signal tracing tied to the RTL) could pre-narrow
the candidate signals before manual inspection, versus cases
subtle enough that it still needs an engineer's judgment call.
Help me structure a debugging approach for a failing simulation
where [describe symptom, e.g. output signal doesn't match
expected value at time X]. Suggest which signals to trace first,
likely root cause categories, and how to narrow down the issue
systematically, and note where an AI/LLM-based waveform-tracing
agent (AST-based signal tracing tied to the RTL) could pre-narrow
the candidate signals before manual inspection, versus cases
subtle enough that it still needs an engineer's judgment call.
16. Regression Test Suite Organization (LLM Test-Gen Aware)
VERIFICATIONStandard regression suite structure, plus where LLM-assisted test generation fits into keeping it current.
Organize a regression test suite structure for
[project/DUT description]. Include test categorization (smoke,
nightly, full regression), pass/fail tracking approach, and
how to prioritize tests after a design change, and note where
an LLM-assisted test-generation step could draft new directed
tests from an RTL diff or spec change, with the requirement
that any AI-generated test is reviewed and understood by a
verification engineer before being trusted in the suite.
Organize a regression test suite structure for
[project/DUT description]. Include test categorization (smoke,
nightly, full regression), pass/fail tracking approach, and
how to prioritize tests after a design change, and note where
an LLM-assisted test-generation step could draft new directed
tests from an RTL diff or spec change, with the requirement
that any AI-generated test is reviewed and understood by a
verification engineer before being trusted in the suite.
17. Formal Verification Property Ideas (Incl. Security Properties)
VERIFICATIONSafety and liveness properties, plus the security-focused properties now standard on any block handling sensitive data.
Suggest properties well-suited for formal verification (rather
than simulation) for [design block description, e.g. an
arbiter or FIFO]. Include safety properties, liveness
properties, and reasons formal analysis fits this block well,
and if this block handles keys, credentials, or privileged
control paths, add security properties to check (information-
flow isolation between trust domains, absence of an
unauthorized bypass path/hardware-Trojan-style trigger) as a
third property category.
Suggest properties well-suited for formal verification (rather
than simulation) for [design block description, e.g. an
arbiter or FIFO]. Include safety properties, liveness
properties, and reasons formal analysis fits this block well,
and if this block handles keys, credentials, or privileged
control paths, add security properties to check (information-
flow isolation between trust domains, absence of an
unauthorized bypass path/hardware-Trojan-style trigger) as a
third property category.
18. Synthesis Constraints (SDC) Draft (Chiplet-Aware)
EDA AUTOMATIONStandard SDC constraints, plus die-to-die interface timing if this block sits on a chiplet.
Draft an SDC constraints outline for a design running at
[target frequency] with clock named [clock name].
Include clock definition, input/output delay constraints, and
false path/multicycle path considerations to review with the
synthesis engineer, and if this block interfaces across a
chiplet/die-to-die boundary (UCIe or similar), add the
additional interface-timing and clock-domain-crossing
constraints that boundary requires.
Draft an SDC constraints outline for a design running at
[target frequency] with clock named [clock name].
Include clock definition, input/output delay constraints, and
false path/multicycle path considerations to review with the
synthesis engineer, and if this block interfaces across a
chiplet/die-to-die boundary (UCIe or similar), add the
additional interface-timing and clock-domain-crossing
constraints that boundary requires.
19. Synthesis Script Structure (TCL) with QoR Review Step
EDA AUTOMATIONA synthesis flow script plus a checkpoint for where an LLM-assisted QoR review can flag issues before P&R.
Draft a TCL script structure for synthesizing
[design name] targeting [technology library/FPGA].
Include steps for reading RTL, applying constraints, running
synthesis, and generating reports, organized as clear
commented sections, and add a QoR-review checkpoint after
synthesis where an LLM-assisted report summarizer highlights
timing/area/power outliers worth a human look before the
design proceeds to place-and-route.
Draft a TCL script structure for synthesizing
[design name] targeting [technology library/FPGA].
Include steps for reading RTL, applying constraints, running
synthesis, and generating reports, organized as clear
commented sections, and add a QoR-review checkpoint after
synthesis where an LLM-assisted report summarizer highlights
timing/area/power outliers worth a human look before the
design proceeds to place-and-route.
20. Timing Report Analysis Approach (AI-Prioritized Fixes)
EDA AUTOMATIONStandard STA triage, plus how an AI-ranked violation list changes the fix order on a large design.
Help me structure a review approach for a static timing
analysis report showing [describe violation, e.g. setup
violations on a specific path]. Suggest what to check first
(logic depth, clock skew, false paths) and how to prioritize
fixing the worst offenders, and note how an AI-assisted
violation-clustering pass (grouping violations by shared root
cause across hundreds of paths) changes the fix order compared
to fixing the single worst slack path first.
Help me structure a review approach for a static timing
analysis report showing [describe violation, e.g. setup
violations on a specific path]. Suggest what to check first
(logic depth, clock skew, false paths) and how to prioritize
fixing the worst offenders, and note how an AI-assisted
violation-clustering pass (grouping violations by shared root
cause across hundreds of paths) changes the fix order compared
to fixing the single worst slack path first.
21. Floorplanning Strategy Overview (Chiplet/3D-IC & AI Placement)
EDA AUTOMATIONFloorplanning fundamentals, extended to chiplet/2.5D-3D IC thermal considerations and AI-driven macro placement.
Summarize floorplanning strategy considerations for a
[chip/block description] with [number] major functional
blocks. Include macro placement guidance, power grid planning,
and I/O pad ring considerations relevant to the design, note
where an AI-driven placement tool (reinforcement-learning-based
macro placement) is worth using over manual placement at this
block count, and if this design spans multiple dies in a
2.5D/3D chiplet package, add thermal co-simulation and
interposer routing-channel considerations across die boundaries.
Summarize floorplanning strategy considerations for a
[chip/block description] with [number] major functional
blocks. Include macro placement guidance, power grid planning,
and I/O pad ring considerations relevant to the design, note
where an AI-driven placement tool (reinforcement-learning-based
macro placement) is worth using over manual placement at this
block count, and if this design spans multiple dies in a
2.5D/3D chiplet package, add thermal co-simulation and
interposer routing-channel considerations across die boundaries.
22. DRC Debug Approach (Advanced-Node Aware)
EDA AUTOMATIONDRC debugging fundamentals, plus the added complexity at 3nm/2nm-class nodes.
Help me structure a debug approach for DRC violations reported
during [layout stage, e.g. place-and-route] involving
[violation type, e.g. spacing, via enclosure].
Suggest common causes for this violation type and a
prioritized order to investigate and fix them, and if this
design targets an advanced node (3nm/2nm-class, gate-all-around
transistors), note which additional multi-patterning and
density-related rule categories tend to generate the most
violations at that node versus an older, more mature node.
Help me structure a debug approach for DRC violations reported
during [layout stage, e.g. place-and-route] involving
[violation type, e.g. spacing, via enclosure].
Suggest common causes for this violation type and a
prioritized order to investigate and fix them, and if this
design targets an advanced node (3nm/2nm-class, gate-all-around
transistors), note which additional multi-patterning and
density-related rule categories tend to generate the most
violations at that node versus an older, more mature node.
23. Regression Automation Script (Python, with LLM Failure Triage)
EDA AUTOMATIONStandard regression automation, plus an LLM-based first-pass triage step on failing logs.
Draft a Python script structure for automating a regression
run across [number] test cases using [simulator name].
Include steps for launching tests in parallel, collecting
pass/fail results, and generating a summary report, and add a
step where an LLM reads failing-test logs and drafts a
first-pass triage summary (likely failure category, similar
past failures) for the verification engineer to confirm rather
than starting the log review from scratch.
Draft a Python script structure for automating a regression
run across [number] test cases using [simulator name].
Include steps for launching tests in parallel, collecting
pass/fail results, and generating a summary report, and add a
step where an LLM reads failing-test logs and drafts a
first-pass triage summary (likely failure category, similar
past failures) for the verification engineer to confirm rather
than starting the log review from scratch.
24. Power Analysis Review Notes (Package/3D-IC Thermal-Aware)
EDA AUTOMATIONStandard dynamic power review, plus the package-level thermal picture that matters once dies are stacked.
Summarize the key factors for reviewing a power analysis
report for [design block] showing [describe result, e.g. higher
than expected dynamic power]. Include switching activity,
clock tree power contribution, and areas to investigate for
reduction, and if this block sits in a stacked/3D-IC package,
note why a package-level thermal co-analysis (heat from
neighboring dies, not just this die's own power map) is needed
in addition to the single-die power report.
Summarize the key factors for reviewing a power analysis
report for [design block] showing [describe result, e.g. higher
than expected dynamic power]. Include switching activity,
clock tree power contribution, and areas to investigate for
reduction, and if this block sits in a stacked/3D-IC package,
note why a package-level thermal co-analysis (heat from
neighboring dies, not just this die's own power map) is needed
in addition to the single-die power report.
25. Design Documentation Template (LLM-RTL-Ready Spec)
EDA AUTOMATIONA hardware spec template written precisely enough to also serve as input to an LLM-based RTL-generation tool.
Create a design specification documentation template for
[design block name]. Include sections for overview, interface
definition, register map (if applicable), timing diagrams
description, and known limitations for other engineers to
reference, and write the interface and behavior sections at a
level of unambiguous, structured detail that could also be fed
into an LLM-based RTL-generation tool, since vague natural-
language specs are the main reason generated RTL doesn't match
intended behavior.
Create a design specification documentation template for
[design block name]. Include sections for overview, interface
definition, register map (if applicable), timing diagrams
description, and known limitations for other engineers to
reference, and write the interface and behavior sections at a
level of unambiguous, structured detail that could also be fed
into an LLM-based RTL-generation tool, since vague natural-
language specs are the main reason generated RTL doesn't match
intended behavior.
AI Prompt Templates for VLSI & Hardware Design Work
Use these AI prompt templates to draft RTL module structure, plan verification testbenches, and organize EDA automation scripts. These prompts are designed to help hardware engineers, verification engineers, and students move faster through early-stage design and documentation always subject to simulation, synthesis, and review by an experienced engineer.
How Can AI Prompts Improve VLSI & Hardware Design Work?
AI prompts improve VLSI and hardware design work by helping structure Verilog/SystemVerilog module design, plan testbench architecture and coverage models, and draft EDA tool scripts for synthesis and analysis. They speed up early-stage thinking while final RTL and constraints remain subject to simulation, synthesis, and review by an experienced engineer.
Frequently Asked Questions
What was updated on this page for September 2026?
This page was refreshed on September 06, 2026 with updated prompt wording, cleaner formatting, and improved guidance so readers can quickly find the most useful AI prompt templates.
What are AI prompts for VLSI and hardware design?
AI prompts for VLSI and hardware design are structured instructions that help AI assist with Verilog/SystemVerilog code structure, verification planning, and EDA automation scripting.
Can AI prompts write production-ready RTL code?
AI prompts can draft RTL structure and testbenches, but all code must be simulated, synthesized, and reviewed by an experienced hardware engineer before tapeout or production use.
Are these prompts beginner-friendly?
Yes. Students and early-career hardware engineers can use these prompts to structure their thinking, though results should always be verified through simulation.
Which AI tools work best for VLSI and hardware design prompts?
These prompts work well with tools like ChatGPT, Claude, and other AI platforms, often alongside simulators and EDA tools such as Verilator, VCS, and industry synthesis tools.
Can these prompts help with EDA tool scripting?
Yes. They can help draft TCL/Python scripting structure and flow automation ideas for synthesis, place-and-route, and verification tool chains.
